circuit Count :
  module Count :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip en : UInt<1>, valid : UInt<1>, out : UInt<8>}

    reg a : UInt<8>, clock with :
      reset => (reset, UInt<8>("h0")) @[Counter.scala 62:40]
    wire b : UInt<1>
    b <= UInt<1>("h0")
    when io.en : @[Counter.scala 120:16]
      node wrap_wrap = eq(a, UInt<8>("he8")) @[Counter.scala 74:24]
      node _wrap_value_T = add(a, UInt<1>("h1")) @[Counter.scala 78:24]
      node _wrap_value_T_1 = tail(_wrap_value_T, 1) @[Counter.scala 78:24]
      a <= _wrap_value_T_1 @[Counter.scala 78:15]
      when wrap_wrap : @[Counter.scala 88:20]
        a <= UInt<1>("h0") @[Counter.scala 88:28]
      b <= wrap_wrap @[Counter.scala 120:23]
    io.out <= a @[Count.scala 21:12]
    io.valid <= b @[Count.scala 22:12]

